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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a low power mixer 3 v receiver if subsystem AD61009 features complete receiver-on-a-chip: monoceiver ? mixer C15 dbm 1 db compression point C8 dbm input third order intercept 500 mhz rf and lo bandwidths linear if amplifier linear-in-db gain control manual gain control quadrature demodulator on-board phase-locked quadrature oscillator demodulates ifs from 1 mhz to 12 mhz can also demodulate am, cw, ssb low power 25 mw at 3 v cmos compatible power-down applications gsm and tetra receivers satellite terminals battery-powered communications receivers pin configuration 20-lead ssop (rs suffix) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD61009 fdin qout iout fltr vps1 com1 prup loip ifop dmip vps2 rflo rfhi gref mxop vmid ifhi iflo gain com2 general description the AD61009 is a 3 v low power receiver if subsystem for opera- tion at input frequencies as high as 500 mhz and ifs from 400 khz to 12 mhz. it consists of a mixer, if amplifiers, i and q demodulators, a ph ase-locked quadrature oscillator, and a biasing system with external power-down. the AD61009? low noise, high intercept mixer is a doubly- balanced gilbert cell type. it has a nominal ?5 dbm input referred 1 db compression point and a ? dbm input referred third-order inte rcept. the mixer section of the ad 61009 also includes a local oscillator (lo) preamplifier, which lowers the required lo drive to ?6 dbm. in mgc operation, the AD61009 accepts an external gain- control voltage input from an external agc detector or a dac. a quadrature vco phase-locked to the if drives the i and q demodulators. the i and q demodulators can also dem odu- late am; when the AD61009? quadrature vco is phase locked to the received signal, the in-phase demodulator becomes a synchronous product detector for am. the vco can also be phase-locked to an external beat-frequency oscillator (bfo), and the demodulator serves as a product detector for cw or ssb reception. finally, the AD61009 can be used to demodu- late bpsk using an external costas loop for carrier recovery. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 monoceiver is a registered trademark of analog devices, inc.
AD61009?pecifications rev. 0 C2C (@ t a = 25 c, supply = 3.0 v, if = 10.7 mhz, unless otherwise noted) model AD61009ars conditions min typ max unit dynamic performance mixer maximum rf and lo frequency range for con version gain > 20 db 500 mhz maximum mixer input voltage for linear operation; between rfhi and rflo 54 mv input 1 db compression point rf input terminated in 50 ? ?5 dbm input third-order intercept rf input terminated in 50 ? ? dbm noise figure mat ched input, max gain, f = 83 mhz, if = 10.7 mhz 14 db matched input, max gain, f = 144 mhz, if = 10.7 mhz 12 db maximum output voltage at mxop z if = 165 ? , at input compression 1.3 v mixer output bandwidth at mxop ? db, z if = 165 ? 45 mhz lo drive level mixer lo input terminated in 50 ? ?6 dbm lo input impedance loip to vmid 1 k ? isolation, rf to if rf = 240 mhz, if = 10.7 mhz, lo = 229.3 mhz 30 db isolation, lo to if rf = 240 mhz, if = 10.7 mhz, lo = 229.3 mhz 20 db isolation, lo to rf rf = 240 mhz, if = 10.7 mhz, lo = 229.3 mhz 40 db isolation, if to rf rf = 240 mhz, if = 10.7 mhz, lo = 229.3 mhz 70 db if amplifiers noise figure max gain, f = 10.7 mhz 17 db input 1 db compression point if = 10.7 mhz ?5 dbm output third-order intercept if = 10.7 mhz 18 dbm maximum if output voltage at ifop z if = 600 ? 560 mv output resistance at ifop from ifop to vmid 15 ? bandwidth ? db at ifop, max gain 45 mhz gain control (see figures 10 and 11) gain control range mixer + if section, gref to 1.5 v 90 db gain scaling gref to 1.5 v 20 mv/db gref to general reference voltage v r 75/v r db/v gain scaling accuracy gref to 1.5 v, 80 db span 1db bias current at gain 5 a bias current at gref 1 a input resistance at gain, gref 1m ? i and q demodulators required dc bias at dmip vpos/2 v dc input resistance at dmip from dmip to vmid 50 k ? input bias current at dmip 2 a maximum input voltage if > 3 mhz 150 mv if 3 mhz 75 mv amplitude balance if = 10.7 mhz, outputs at 600 mv p-p, f = 100 khz 0.2 db quadrature error if = 10.7 mhz, outputs at 600 mv p-p, f = 100 khz ?.5 ?.2 +1.5 degrees phase noise in degrees if = 10.7 mhz, f = 10 khz ?00 dbc/hz demodulation gain sine wave input, baseband output 17.4 18 18.8 db maximum output voltage r l 20 k ? 1.23 v output offset voltage measured from i out , q out to vmid ?00 10 +100 mv output bandwidth sine wave input, baseband output 1.5 mhz pll required dc bias at fdin vpos/2 v dc input resistance at fdin from fdin to vmid 50 k ? input bias current at fdin 200 na frequency range 1.0 to 12 mhz required input drive level sine wave input at pin 1 400 mv acquisition time to 3 if = 10.7 mhz 16.5 s power-down interface logical threshold for power up on logical high 2 v dc input current for logical high 75 a turn-on response time to pll locked 16.5 s standby current 550 a power supply supply range 2.85 5.5 v supply current 8.5 12.5 ma operating temperature t min to t max operation to 2.85 v minimum supply voltage ?5 +85 c operation to 4.5 v minimum supply voltage ?0 +85 c specifications subject to change without notice.
AD61009 rev. 0 C3C absolute maximum ratings 1 supply voltage vps1, vps2 to com1, com2 . . . . . . . 5.5 v internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 600 mw 2.7 v to 5.5 v operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 c to +85 c 4.5 v to 5.5 v operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c ordering guide model temperature range package description package option AD61009ars 25 c to +85 c for 2.7 v to 5.5 v 20-lead plastic ssop rs-20 operation; ?0 c to +85 c for 4.5 v to 5.5 v operation caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD61009 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device notes 1 stresses above those listed under absolute maximum rating may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 thermal characteristics: 20-lead ssop package: ja = 126 c/w.
rev. 0 C4C AD61009 pin function descriptions pin mnemonic reads function 1 fdin frequency detector input pll input for i/q demodulator quadrature oscillator, 400 mv drive required from external oscillator. must be biased at v p /2. 2 com1 common #1 supply common for rf front end and main bias. 3 prup power-up input 3 v/5 v cmos compatible power-up control; logical high = powered-up; max input level = vps1 = vps2. 4 loip local oscillator input lo input, ac coupled 54 mv lo input required (?6 dbm for 50 ? input termination). 5 rflo rf ?ow?input usually connected to ac ground. 6 rfhi rf ?igh?input ac coupled, 56 mv, max rf input for linear operation. 7 gref gain reference input high impedance input, typically 1.5 v, sets gain scaling. 8 mxop mixer output high impedance, single-sided current output, 1.3 v max voltage output ( 6 ma max current output). 9 vmid midsupply bias voltage output of the midsupply bias generator (vmid = vpos/2). 10 ifhi if ?igh?input ac coupled if input, 56 mv max input for linear operation. 11 iflo if ?ow?voltage reference node for if input; auto-offset null. 12 gain gain control input high impedance input, 0 v? v using 3 v supply, max gain at v = 0. 13 com2 common #2 supply common for if stages and demodulator. 14 ifop if output low impedance, single-sided voltage output, 5 dbm ( 560 mv) max. 15 dmip demodulator input signal input to i and q demodulators 150 mv max input at if > 3 mhz for linear operation; 75 mv max input at if < 3 mhz for linear operation. must be biased at v p /2. 16 vps2 vpos supply #2 supply to high-level if, pll, and demodulators. 17 qout quadrature output low impedance q baseband output; 1.23 v full scale in 20 k ? min load; ac coupled. 18 iout in-phase output low impedance i baseband output; 1.23 v full scale in 20 k ? min load; ac coupled. 19 fltr pll loop filter series rc pll loop filter, connected to ground. 20 vps1 vpos supply #1 supply to mixer, low level if, pll, and gain control. pin connection 20-lead ssop (rs-20) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD61009 fdin qout iout fltr vps1 com1 prup loip ifop dmip vps2 rflo rfhi gref mxop vmid ifhi iflo gain com2
hp8656b ieee rf_out synthesizer hp8656b ieee rf_out synthesizer hp8656b ieee rf_out synthesizer hp6633a ieee vpos vneg spos sneg dcps hp34401a cpib hi lo i dmm dp8200 ieee vpos vneg spos sneg v ref hp8764b 0 0 1 1 s0 s1 v 50 50 mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain hp8764b 0 0 1 1 s0 s1 v 50 50 hp8594e rf_in ieee spec an hp8765b 0 1 c s0 s1 v r5 1k characterization board hp8765b 0 1c s0 s1 v p6205 x10 out fet probe tek1105 in1 out1 in2 out2 probe supply tpc 1. mixer/amplifier test set hp346b 28v noise noise source hp8656b ieee rf_out synthesizer mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain hp8765b 0 1 c s0 s1 v 50 characterization board hp8765b 0 1c s0 s1 v hp8720c ieee_488 port_1 port_2 network an hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref hp8970a rf_in 28v_out noise figure meter tpc 2. mixer noise figure test set typical performance characteristics AD61009 rev. 0 C5C
rev. 0 C6C AD61009 hp346b 28v noise noise source mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref hp8970a rf_in 28v_out noise figure meter p6205 x10 out fet probe tek1103 in1 out1 in2 out2 probe supply tpc 3. if amp noise figure test set mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board hp8764b 0 0 1 1 s0 s1 v 50 50 hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref hp3326a ieee output_1 output_2 dual synthesizer dcfm hp8656b ieee rf_out synthesizer p6205 x10 fet probe p6205 x10 fet probe out out 1103 out1 out2 probe supply hp8765b 0 1 c s0 s1 v hp8765b 0 1c s0 s1 v hp8694e rf_in ieee spec an hp54120 ch1 digital oscilloscope ch2 ch3 ch4 trig ieee_488 in1 in2 tpc 4. pll/demodulator test set
AD61009 rev. 0 C7C dp8200 ieee vpos vneg spos sneg v ref hp34401a gpib hi lo i dmm hp6633a ieee vpos vneg spos sneg dcps r1 499k mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board tpc 5. gain pin bias test set dp8200 ieee vpos vneg spos sneg v ref hp34401a gpib hi lo i dmm hp6633a ieee vpos vneg spos sneg dcps r1 499k mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board tpc 6. demodulator bias test set hp6633a ieee vpos vneg spos sneg dcps hp34401a gpib hi lo i dmm hp6633a ieee vpos vneg spos sneg dcps r1 10k hp3325b ieee rf_out synthesizer hp8594e rf_in ieee spec an mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board tpc 7. power-up threshold test set
rev. 0 C8C AD61009 hp6633a ieee vpos vneg spos sneg dcps fl6082a rf_out ieee mod_out dp8200 ieee vpos vneg spos sneg v ref hp8112 pulse_out ieee pulse generator hp54120 ch1 ch2 ch3 ch4 trig ieee_488 p6205 x10 out fet probe 1103 in1 out1 in2 out2 probe supply p6205 x10 out fet probe 50 digital oscilloscope note: must be 3 resistor power divider mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board tpc 8. power-up test set hp8594e rf_in ieee spec an p6205 x10 out fet probe 1103 in1 out1 in2 out2 probe supply hp6633a ieee vpos vneg spos sneg dcps hp8656b rf_out ieee synthesizer r1 1k mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board tpc 9. if output impedance test set
AD61009 rev. 0 C9C hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref p6205 x10 fet probe p6205 x10 fet probe out out 1103 out1 out2 probe supply hp54120 ch1 digital oscilloscope ch2 ch3 ch4 trig ieee_488 in1 in2 fl6082a ieee rf_out mod_out 20 db mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin vpos prup gain characterization board bias tpc 10. pll settling time test set hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref hp3326 ieee output_1 output_2 dual synthesizer dcfm hp3325b ieee rf_out synthesizer p6205 x10 fet probe p6205 x10 fet probe out out 1103 out1 out2 probe supply hp8765b 0 1c s0 s1 v hp8694e rf_in ieee spec an in1 in2 mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin vpos prup gain characterization board bias tpc 11. quadrature accuracy test set
rev. 0 C10C AD61009 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 AD61009 fdin qout iout fltr vps1 com1 prup loip ifop dmip vps2 rflo rfhi gref mxop vmid ifhi iflo gain com2 0.1 f c13 c15 0.1 f iout * qout * ifop * gain * dmip * 0.1 f c1 c3 10nf r1 1k r2 316 c6 0.1 f c8 0.1 f c5 1nf 4.99k r10 r8 51.1 c11 10nf r7 51.1 c10 1nf r6 51.1 c9 1nf r14 54.9 r13 301 r5 332 0.1 f vpos gnd fdin prup loip rfhi mxop * ifhi 0 r12 c16 1nf c7 1nf 0.1 f c2 note: connections marked * are dc coupled. r9 51.1 tpc 12. characterization board
AD61009 rev. 0 C11C rf frequency ?mhz ssb nf ?db 20 18 10 50 250 70 90 110 130 150 170 190 210 230 16 14 12 19 17 15 13 11 vpos = 5v, if = 20mhz vpos = 3v, if = 20mhz vpos = 5v, if = 10mhz vpos = 3v, if = 10mhz tpc 13. mixer noise figure vs. frequency 4500 3000 0 500 250 0 2500 2000 3500 4000 frequency mhz 1500 1000 500 50 100 150 200 300 350 400 450 resistance r shunt component c shunt component 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 capacitance p f tpc 14. mixer input impedance vs. frequency, vpos = 3 v, v gain = 0.8 v 30 20 20 600 300 0 25 10 15 0 5 radio frequency mhz 5 15 10 50 100 150 200 250 350 400 450 500 550 conversion gain db v gain = 0.00v v gain = 0.54v v gain = 1.08v v gain = 1.62v v gain = 2.16v tpc 15. mixer conversion gain vs. frequency, t = 25 c, vpos = 2.7 v, vref = 1.35 v, if = 10.7 mhz 30 20 100 0.1 25 10 15 0 5 intermediate frequency mhz 5 10 110 conversion gain db v gain = 0.3v v gain = 0.6v v gain = 1.8v v gain = 1.2v v gain = 2.4v &'()0 *+
(
3.&=#/ c, vpos = 3 v, vref = 1.5 v 80 60 130 50 70 40 50 20 30 temperature c 10 20 70 0 10 30 10 10 20 30 40 50 60 80 90 100 110 120 40 20 0 gain db cubic fit of conv_gain (temp) cubic fit of if_gain (temp) if amp gain mixer cg tpc 17. mixer conversion gain and if amplifier gain vs. temperature, vpos = 3 v, vgain = 0.3 v, vref = 1.5 v, if = 10.7 mhz, rf = 250 mhz 80 60 6 2.4 70 40 50 20 30 supply volts 10 4.8 gain db 2.8 3.2 3.6 3.8 4 4.2 4.4 4.6 5 5.2 5.4 5.6 5.8 2.6 3 3.4 cubic fit of conv_gain (v pos ) cubic fit of if_gain (v pos ) if amp gain mixer cg tpc 18. mixer conversion gain and if amplifier gain vs. supply volta ge, t = 25 c, vgain = 0.3 v, vref = 1.5 v, if = 10.7 mhz, rf = 250 mhz
rev. 0 C12C AD61009 70 50 100 0.1 60 30 40 10 20 intermediate frequency mhz 0 10 110 if amplifier gain db v gain = 0.3v v gain = 0.6v v gain = 1.8v v gain = 1.2v v gain = 2.4v 80 tpc 19. if amplifier gain vs. frequency, t = 25 c, vpos = 3 v, vref = 1.5 v 8 4 3 0 6 0 2 4 2 gain voltage volts 6 10 12 error db 10 8 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8 if amp mixer tpc 20. gain error vs. gain control voltage, representative part 996.200 s 1.00870ms 1.02120ms trigger on external at pos. edge at 134.0mv timebase memory 1 timebase memory 2 timebase delta t start = 2.5 s/div = 100.0mv/div = 2.50 s/div = 20.00mv/div = 2.50 s/div = 16.5199 s = 1.00048ms delay offset delay offset delay stop = 1.00870ms = 127.3mv = 1.00870ms = 155.2mv = 1.00870ms = 1.01700ms tpc 21. pll acquisition time 1.00e+07 1.00e+02 110.00 100.00 130.00 120.00 carrier frequency offset , f ( fm ) hz 140.00 150.00 1.00e+03 1.00e+05 90.00 1.00e+04 1.00e+06 phase noise dbc tpc 22. pll phase noise l (f) vs. frequency, vpos = 3 v, c3 = 0.1 f, if = 10.7 mhz 100 0.1 2 pll frequency mhz 1.5 110 fltr pin voltage volts 2.5 tpc 23. pll loop voltage at fltr (k vco ) vs. frequency 8 5 94 85 7 3 4 1 2 quadrature angle degrees 0 91 86 87 88 89 90 92 93 6 95 count tpc 24. demodulator quadrature angle, histogram, t = 25 c, vpos = 3 v, if = 10.7 mhz
AD61009 rev. 0 C13C 30 20 2 25 10 15 5 iq gain balance db 0 count 10 1 2 tpc 25. demodulator gain balance, histogram, t = 25 c, vpos = 3 v, if = 10.7 mhz 20 18 0 19 16 17 15 baseband frequency mhz 10 0.2 0.4 0.6 0.8 14 12 13 11 1.0 1.2 1.4 1.6 1.8 2.0 igain db quadratic fit of i_gain_corr (iff) i_gain_corr tpc 26. demodulator gain vs. frequency 20 18 50 19 16 17 15 temperature c 10 40 30 20 10 14 12 13 11 0 1020304050 igain db cubic fit of i_gain_corr (temp) i_gain_corr 60 70 80 90 100 110 120 130 tpc 27. demodulator gain vs. temperature 20 18 2.5 19 16 17 15 supply volts 10 3 14 12 13 11 3.5 4 4.5 igain db cubic fit of i_gain_corr (temp) i_gain_corr 5 5.5 6 tpc 28. demodulator gain vs. supply voltage 40 25 17 35 15 20 10 demodulator gain db 0 17.2 5 17.4 17.6 17.8 18 18.2 18.4 count 18.6 18.8 30 tpc 29. demodulator gain histogram, t = 25 c, vpos = 3 v, if = 10.7 mhz 40.2127ms 40.2377ms 40.2627ms trigger on external at pos. edge at 40.0mv timebase memory 1 timebase memory 2 timebase delta t start = 500 s/div = 100.0mv/div = 5.00 s/div = 60.00mv/div = 5.00 s/div = 15.7990 s = 40.2327ms delay offset delay offset delay stop = 40.2377ms = 154.0mv = 40.2377ms = 209.0mv = 40.2377ms = 40.2485ms tpc 30. power-up response time to pll stable
rev. 0 C14C AD61009 product overview the AD61009 provides most of the active circuitry required to realize a complete low power, single-conversion superheterodyne receiver, or most of a double-conversion receiver, at input fre- quencies up to 500 mhz, and with an if of from 400 khz to 12 mhz. the internal i/q demodulators, and their associated phase locked-loop, which can provide carrier recovery from the if, support a wide variety of modulation modes, including n-psk, n-qam, and am. a single positive supply voltage of 3 v is required (2.85 v minimum, 5.5 v maximum) at a typical supply c urrent of 8.5 ma at midgain. in the following discus- sion, v p will be used to denote the power supply voltage, which will be assumed to be 3 v. figure 1 shows the main sections of the AD61009. it consists of a variable-gain uhf mixer and linear four-stage if strip, which toge ther provide a voltage controlled gain range of more than 90 db; followed by dual demodulators, each comprising a multi- plier followed by a two-pole, 2 mhz low-pass filter; and driven by a phase-locked loop providing the inphase and quadrature clocks. a biasing system with cmos compatible power-down completes the AD61009. rfhi rflo iflo bpf loip mxop midpoint bias generator vmid ifhi bias generator vps1 vps2 prup com1 com2 vmid ptat voltage ifop bpf or lpf dmip iout fdin fltr qout gain AD61009 gref vqfo figure 1. functional block diagram 0 gain voltage volts 5 0.5 1.5 2 10 1 15 2.5 supply current ma tpc 31. power supply current vs. gain control voltage, gref = 1.5 v mixer the uhf mixer is an improved gilbert cell de sign, and can operate from low frequencies (it is internally dc-coupled) up to an rf input of 500 mhz. the dynamic range at the input of the mixer is determined, at the upper end, by the maximum input signal level of 56 mv between rfhi and rflo up to which the mixer remains linear, and, at the lower end, by the noise level. it is customary to define the linearity of a mixer in terms of the 1 db gain-compression point and third-order intercept, which for the AD61009 are 15 dbm and ? dbm, respectively, in a 50 ? system. the mixer? rf input port is differential, that is, pin rflo is functionally identical to rfhi, and these nodes are internally biased; we will generally assume that rflo is decoupled to ac ground. the rf port can be modeled as a parallel rc circuit as shown in figure 2. r in c in c2 c1 c3 l1 rfhi rflo AD61009 c1, c2, l1: optional matching circuit c3: couples rflo to ac ground figure 2. mixer port modeled as a parallel rc network; an optional matching network is also shown the local oscillator (lo) input is internally biased at v p /2 via a nominal 1000 ? resistor internally connected from pin loip to vmid. the lo interface includes a preamplifier which minimizes the drive requirements, thus simplifying the oscillator design and reducing lo leakage from the rf port. internally, this single-sided input is actually differential; the noninverting input is referenced to pin vmid. the lo requires a single-sided drive of 50 mv, or ?6 dbm in a 50 ? system.
AD61009 rev. 0 C15C the mixer? output passes through both a low-pass filter and a buffer, which provides an internal differential to single-ended signal conversion with a bandwidth of approximately 45 mhz. its output at pin mxop is in the form of a single-ended current. this approach elim inates the 6 db volt age loss of the usual series termination by replacing it with shunt terminations at the both the input and the output of the filter. the nominal conversion gain is specified for operation into a total if bandpass filter (bpf) load of 165 ? , that is, a 330 ? filter, doubly-terminated as shown in figure 33. note that these loads are connected to bias point vmid, which is always at the midpoint of the supply (that is, v p /2). the conversion gain is measured between the mixer input and the input of this filter, and varies between 1.5 db and 26.5 db for a 165 ? load impedance. using filters of higher impedance, the conversion gain can always be maintained at its specified value or made even higher; for filters of lower impedance, of say z o , the conversion gain will be lowered by 10 log 10 (165/z o ). thus, the use of a 50 ? filter will result in a conversion gain that is 5.2 db lower. figure 3 shows filter matching networks and table i lists resistor values. iflo bpf mxop vmid ifhi 10 11 8 9 1nf 100nf r3 100nf r1 r2 figure 3. sugge sted if filter matching netwo rk. the values of r1 and r2 are selected to keep the impedance at pin mxop at 165 ? table i. AD61009 filter termination resistor values for common ifs filter filter termination resistor if impedance values 1 for 24 db of mixer gain r1 r2 r3 450 khz 1500 ? 174 ? 1330 ? 1500 ? 455 khz 1500 ? 174 ? 1330 ? 1500 ? 6.5 mhz 1000 ? 215 ? 787 ? 1000 ? 10.7 mhz 330 ? 330 ? 0 ? 330 ? note 1 resistor values were calculated such that r1 + r2 = z filter and r1 (r2 + z filter ) = 165 ? . the maximum permissible signal level at mxop is determined by both voltage and current limitations. using a 3 v supply and vmid at 1.5 v, the maximum swing is about 1.3 v. to attain a voltage swing of 1 v in the standard if filter load of 165 ? load requires a peak drive current of about 6 ma, which is well within the linear capability of the mixer. however, these upper limits for voltage and current should not be confused with issues related to the mixer gain, already discussed. in an operational system, the agc voltage will determine the mixer gain, and hence the signal level at the if input pin ifhi; it will always be less than 56 mv (?5 dbm into 50 ? ), which is the limit of the if amplifier? linear range. if amplifier most of the gain in the AD61009 arises in the if amplifier strip, which comprises four stages. the first three are fully differential and each has a gain span of 25 db for the nominal agc voltage range. thus, in conjunction with the mixer? variable gain, the total gain exceeds 90 db. the final if stage has a fixed gain of 20 db, and it also provides differential to single-ended con version. the if input is differential, at ifhi (noninverting relative to the output ifop) and iflo (inverting). figure 4 shows a simplified schematic of the if interface. the offset voltage of this stage would cause a large dc output error at high gain, so it is n ulled by a low-pass feedback path from the if output, also shown in tpc 25. un like the mixer output, the signal at ifop is a low- impedance single-sided voltage, centered at v p /2 by the dc feedback loop. it may be loaded by a resistance as low as 50 ? , which will normally be connected to vmid. 10k 10k vmid AD61009 ifhi iflo offset feedback loop ifop figure 4. simplified schematic of the if interface the if? small-signal bandwidth is approximately 45 mhz from ifhi and iflo through ifop. the peak output at ifop is 560 mv at v p = 3 v and 400 mv at the minimum v p of 2.7 v. this allows some headroom at the demodulator inputs (pin dmip), which accept a maximum input of 150 mv for ifs > 3 mhz and 75 mv for ifs 3 mhz (at ifs 3 mhz, the drive to the demodulators must be reduced to avoid saturat- ing the output amplifiers with higher order mixing products that are no longer removed by the onboard low-pass filters).
rev. 0 C16C AD61009 since there is no band-limiting in the if strip, the output- referred noise can be quite high; in a typical application and at a gain of 75 db it is about 100 mv rms, making post-if filtering desirable. ifop may be also used as an if output for driving an a/d converter, external demodulator, or external agc detector. figure 5 shows methods of matching the optional second if filter. AD61009 bpf ifop dmip r t 2r t 2r t vpos a. biasing dmip from power supply (assumes bpf ac coupled internally) AD61009 bpf ifop dmip r t vmid r t c bypass b. biasing dmip from vmid (assumes bpf ac coupled internally) figure 5. input and output matching of the optional second if filter gain scaling and rssi the AD61009? overall gain, expressed in decibels, is linear- in-db w ith respect to the agc voltage v g at pin gain. the gain of all sections is maximum when v g is zero, and reduces progressively up to v g = 2.2 v (for v p = 3 v; in general, up to a limit v p ?0.8 v). the gain of all stages changes in parallel. the AD61009 features temperature-compensation of the gain scal- ing. the gain control scaling is proportional to the reference voltage applied to the pin gref. when this pin is tied to the midpoint of the su pply (vmid), the scale is nominally 20 mv/ db (50 db/v) for v p = 3 v. under these conditions, the lower 80 db of gain range (mixer plus if) corresponds to a control voltage of 0.4 v v g 2.0 v. the final centering of this 1.6 v range depends on the insertion losses of the if filters used. more generally, the gain scaling using these connections is v p /150 (volts per db), so becomes 33.3 mv/db (30 db/v) using a 5 v supply, with a proportional change in the agc range, to 0.33 v v g 3 v, table ii lists gain control voltages and scale factors for power supply voltages from 3 v to 5.5 v. alternatively, pin gref can be tied to an external voltage reference, v r , provided, for example, by an ad1582 (2.5 v) or ad1580 (1.21 v) voltage reference, to provide supply- independent gain scaling of v r /75 (volts per db). since it uses the same reference voltage, the numerical input to this dac provides an accurate rssi value in digital form, no longer requiring the reference voltage to have high absolute accuracy. i/q demodulators both demodulators (i and q) receive their inputs at pin dmip. internally, this single-sided input is actually differential; the noninverting input is referenced to pin vmid. each demodula- tor comprises a full-wave synchronous detector followed by a 2 mhz, two-pole low-pass filter, producing single-sided outputs at pins iout and qot. using the i and q demodulators for ifs above 12 mhz is precluded by the 1 mhz to 12 mhz response of the pll used in the demodulator section. pin dmip requires an external bias source at v p /2; figure 6 shows sug- gested methods. outputs iout and qout are centered at v p /2 and can swing up to 1.23 v even at the low supply voltage of 2.85 v. the conversion gain of the i and q demodulators is 18 db (x8), requiring a maximum input amplitude at dmip of 150 mv for ifs > 3 mhz. table ii. AD61009 gain and manual gain control voltage vs. power supply voltage power supply gref gain control voltage (= vmid) scale factor scale factor voltage input range (v) (v) (db/v) (mv/db) (v) 3.0 1.5 50.00 20.00 0.400?.000 3.5 1.75 42.86 23.33 0.467?.333 4.0 2.0 37.50 26.67 0.533?.667 4.5 2.25 33.33 30.00 0.600?.000 5.0 2.5 30.00 33.33 0.667?.333 5.5 2.75 27.27 36.67 0.733?.667 note maximum gain occurs for gain control voltage = 0 v.
AD61009 rev. 0 C17C AD61009 bpf ifop dmip r t 2r t 2r t vpos a. biasing dmip from power supply (assumes bpf ac-coupled internally) AD61009 bpf ifop dmip r t vmid r t c bypass b. biasing dmip from vmid (assumes bpf ac-coupled internally) figure 6. suggested methods for biasing pin dmip at v p /2 for ifs < 3 mhz, the on-chip low-pass filters (2 mhz cutoff) do not attenuate the if or feedthrough products; thus, the maximum input voltage at dmip must be limited to 75 mv to allow sufficient headroom at the i and q outputs for not only the desired baseband signal but also the unattenuated higher- order demodulation products. these products can be removed by an external low-pass filter. phase-locked loop the demodulators are driven by quadrature signals that are provided by a variable frequency quadrature oscillator (vfqo), phase locked to a reference signal applied to pin fdin. when this signal is at the if, inphase and quadrature baseband outputs are generated at iout and qout, respectively. the q uadra- ture accuracy of this vfqo is typically ?.2 at 10.7 mhz. the pll uses a sequential-phase detector that comprises low power emitter-coupled logic and a charge pump (figure 7). sequential phase detector variable- frequency quadrature oscillator 90 q-clock (ecl outputs) i-clock reference carrier (fdin after limiting) u d i u ~ 40 a c r v f f r i d ~ 40 a figure 7. simplified schematic of the pll and quadrature vco the reference signal may be provided from an external source, in the form of a high-level clock, typically a low level signal ( 400 mv) since there is an input amplifier between fdin and the loop? phase detector. for example, the if output itself can be used by connecting dmip to fdin, which will then pro vide automatic carrier recover for synchronous am detection and take advantage of any post-if filtering. pin fdin must be biased at v p /2; figure 9 shows suggested methods. the vfqo operates from 1 mhz to 12 mhz and is con trolled by the voltage between vpos and fltr. in normal operation, a series rc network, forming the pll loop filter, is connected from fltr to ground. the use of an integral sample-hold system ensures that the frequency-control voltage on pin fltr remains held during power-down, so reacquisition of the carrier typically occurs in 16.5 s. in practice, the probability of a phase mismatch at power-up is high, so the worst-case linear settling period to full lock needs to be considered in making filter choices. this is typically 16.5 s at an if of 10.7 mhz for a 100 mv signal at dmip and fdin. bias system the AD61009 operates from a single supply, v p , usually of 3 v, at a typical supply current of 8.5 ma at midgain and t = 27 c, corresponding to a power consumption of 25 mw. any voltage from 2.85 v to 5.5 v may be used. the bias system includes a fast-acting active-high cmos- compatible power-up switch, allowing the part to idle at 550 a when disabled. biasing is proportional-to-absolute-temperature (ptat) to ensure stable gain with temperature. an independent regulator generates a voltage at the midpoint of the supply (v p /2) which appears at the vmid pin, at a low impedance. this voltage does not shut down, ensuring that the major signal interfaces (e.g., mixer-to-if and if-to-demodula tors) remain biased at all times, thus minimizing transient distur bances at power-up and allowing the use of substantial decoupling capacitors on this node. the quiescent consumption of this regulator is included in the idling current. AD61009 fdin 50k 50k vpos external frequency reference a. biasing fdin from supply when using external frequency reference AD61009 fdin 50k c bypass external frequency reference vmid b. biasing fdin from vmid when using external frequency reference figure 8. suggested methods for biasing pin fdin at v p /2
rev. 0 C18C AD61009 using the AD61009 in this section, we will focus on a few areas of special impor- tance and include a few general application tips. as is true of any wideband high gain component, great care is needed in pc board layout. the location of the particular grounding points must be considered with due regard to possibility of unwanted signal coupling, particularly from ifop to rfhi or ifhi or both. the high sensitivity of the AD61009 leads to the possibility that unwanted local em signals may have an effect on the performance. during system development, carefully-shielded test assemblies should be used. the best solution is to use a fully-enclosed box enclosing all components, with the minimum number of needed signal connectors (rf, lo, i and q outputs) in min- iature coax form. the i and q output leads can include small series resistors (about 100 ? ) inside the shielded box without significant loss of performance, provided the external loading during testing is light (that is, a resistive load of more than 20 k ? and capaci- tances of a few picofarads). these help to keep unwanted rf emanations out of the interior. the power supply should be connected via a through-hole capacitor with a ferrite bead on both inside and outside leads. close to the ic pins, two capacitors of different value should be used to decouple the main supply (v p ) and the midpoint supply pin, vmid. guidance on these matters is also generally in cluded in applications schematics. gain distribution as in all receivers, the most critical decisions in effectively using the AD61009 relate to the partitioning of gain between the various subsections (mixer, if amplifier, demodulators) and the place ment of filters, so as to achieve the highest overall signal- to-noise ratio and lowest intermodulation distortion. figure 9 shows the main rf/if signal path at maximum and minimum signal levels. as noted earlier, the gain in db is reduced linearly with the voltage v g on the gain pin. figure 10 shows how the mixer and if strip gains vary with v g when gref is connected to vmid (1.5 v) and a supply voltage of 3 v is used. figure 11 shows how these vary when gref is connected to a 1.23 v refere nce. v g (7.5db) (1.5db) 01v2v 0.4v 1.8v 2.2v (67.5db) (21.5db) if gain mixer gain 90db 80db 70db 60db 50db 40db 30db 20db 10db 0db normal operating range figure 10. gain distribution for gref = 1.5 v (7.5db) (1.5db) 01v2v (67.5db) (21.5db) if gain mixer gain 90db 80db 70db 60db 50db 40db 30db 20db 10db 0db 0.328v 1.64v v g normal operating range figure 11. gain distribution for gref = 1.23 v iout qout i q rfhi loip mxop ifhi dmip ifop if bpf if bpf (vmid) 330 330 (typical impedance) (location of optional second if filter) constant 16dbm ( 50mv) 54mv max input 1.3v max output 54mv max input 560mv max output 154mv max input 1.23v max output figure 9. signal levels for minimum and maximum gain
AD61009 rev. 0 C19C using the AD61009 with a fast prup control signal if the AD61009 is used in a system in which the prup signal (pin 3) is applied with a rise time less than 35 s, anomalous behavior occasionally occurs. the problem is intermittent, so it will not occur every time the part is powered up under these condi tions. it does not occur for any other normal operating condi- tions when the prup signal has a rise time slower than 35 s. symptoms of operation with too fast a prup signal include low gain, oscillations at the i or q outputs of the device or no valid data occurring at the output of the AD61009. the problem causes no permanent damage to the AD61009, so it will often operate normally when reset. fortunately, there is a very simple solution to the fast prup problem. if the prup signal (pin 3) is slowed down so that the rise time of the signal edge is greater than 35 s, the anoma- lous behavior will not occur. this can be realized by a simple rc circuit connected to the prup pin, where r = 4.7 k ? and c = 1.5 nf. this circuit is shown in figure 12. AD61009 prup 4.7k 1.5nf from prup control signal figure 12. proper configuration of AD61009 prup signal all designs incorporating the AD61009 should include this circuitry. note that connecting the prup pin to the supply voltage will not eliminate the problem since the supply voltage may have a rise time faster than 35 s. with this configuration, the 4.7 k ? series r and 1.5 nf shunt c should be placed between the supply and the prup pin as shown in figure 12. AD61009 evaluation board the AD61009 evaluation board (figures 13 and 14) consists of an AD61009, ground plane, i/o connectors, and a 10.7 mhz bandpass fi lter. the rf and lo ports are terminated in 50 ? to provide a broadband match to external signal generators to allow a choice of rf and lo input frequencies. the if filter is at 10.7 mhz and has 330 ? input and output terminations; the board is laid out to allow the user to substitute other filters for other ifs. the board provides sma connectors for the rf and lo port inputs, the demodulated i and q outputs, the manual gain con- trol (mgc) input, the pll input, and the power-up input. in addition, the if output is also available at an sma connector; this may be connected to the pll input for carrier recovery to realize synchronous am and fm detection via the i and q demodulators, respectively. table iii lists the AD61009 evalua- tion board? i/o connectors and their functions.
rev. 0 C20C AD61009 vps1 AD61009 c12 0.1 f c5 1nf c6 0.1 f c8 0.1 f gain if q i c1 0.1 f c3 10nf r1 1k c20.1 f c4 47pf r2 316 c15 0.1 f jumper jumper c16 1nf r10 4.99k r11 open c11 10nf r8 51.1 c13 0 c14 0 r7 51.1 r6 51.1 c10 1nf c9 1nf r5 332 r3 332 r4 open c7 1nf vpos gnd fdin prup lo rf ad607 evaluation board (as received) fdin com1 prup loip rflo rfhi gref mxop vmid ifhi fltr iout qout vps2 dmip ifop com2 gain iflo c17 1.5nf r12 4.7k vpos r13 50k r15 50k fdin r12 open vmid c17 10nf c18 short r14 51.1 fdin mod for large magnitude ac-coupled input vpos r18 open r17 open fdin r16 open vmid c20 short c19 anything r19 rsource fdin mod for dc-coupled input figure 13. evaluation board
AD61009 rev. 0 C21C AD61009 evaluation board rev b analog devices rfhi loip prup r12 c17 c13 c10 c11 c16 c9 r7 c14 r6 j9 r4 r5 r3 c7 filt c6 c8 c4 r2 c2 r1 c3 c3' ifop c12 c15 r10 r8 r11 c1 j10 u1 fdin a. topside c5 iout qout r9 gain b. bottom side figure 14. evaluation board layout
rev. 0 C22C AD61009 table iii. AD61009 evaluation board input and output connections reference connector approximate designation type description coupling signal level comments j1 sma frequency dc 400 mv this pin needs to be biased at vmid detector input and ac coupled when driven by an external signal generator. j2 sma power up dc cmos logic tied to positive supply by jumper j10. level input j3 sma lo input ac ?6 dbm input is terminated in 50 ? . ( 50 mv) j4 sma rf input ac ?5 dbm max input is terminated in 50 ? . ( 54 mv) j5 sma mgc input dc 0.4 v to 2.0 v jumper is set for manual gain control (3 v supply) input; see table i for control voltage (gref = vmid) values. j6 sma if output ac na this signal level depends on the AD61009? gain setting. j7 sma q output ac na this signal level depends on the AD61009? gain setting. j8 sma i output ac na this signal level depends on the AD61009? gain setting. j9 jumper ties gref na na sets gain-control scale factor (sf); to vmid sf = 75/vmid in db/v, where vmid = vpos/2. j10 jumper ties power-up na na remove to test power-up/-down. to positive supply t1 terminal pin power supply dc dc 2.85 v to 5.5 v positive input draws 8.5 ma at midgain connection. (vps1, vps2) t2 terminal pin power supply dc 0 v return (gnd)
AD61009 rev. 0 C23C hp 6632a programmable power supply 2.7v 6v hp 3326 synthesized signal generator 10.710mhz fluke 6082a synthesized signal generator 240mhz hp 8656a synthesized signal generator 240.02mhz ad607 evaluation board tektronix 11402a oscilloscope with 11a32 plugin hp 8656a synthesized signal generator 229.3mhz data precision dvc8200 programmable voltage source hp 9920 ieee controller hp9121 disk drive mcl zfsc 2 1 combiner ieee 488 bus vpos fdin i output q output mgc lo rf figure 15. evaluation board test setup in operation (figure 15), the AD61009 evaluation board draws about 8.5 ma at midgain (59 db). use high impedance probes to monitor signals from the demodulated i and q outputs and the if output. the mgc voltage should be set such that the signal level at dmip does not exceed 150 mv; signal levels above this will overload the i and q demodulators. the inser- tion loss between ifop and dmip is typically 3 db if a simple low-pass filter (r8 and c2) is used and higher if a reverse- terminated bandpass filter is used.
rev. 0 C24C AD61009 outline dimensions dimensions shown in inches and (mm). 20-lead plastic ssop (rs-20) 20 11 10 1 0.295 (7.50) 0.271 (6.90) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 c02347C0C1/01 (rev. 0) printed in u.s.a.

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